A) Field of the Invention
The present invention relates to a semiconductor device, and its manufacture method, and more particularly to a semiconductor device having a memory circuit of, for example, non-volatile memory cell transistors and a peripheral circuit of logical cell transistors, and to its manufacture method.
B) Description of the Related Art
Known as the structure of an electrically erasable non-volatile memory, is a structure having a lamination of a floating gate structure having a charge retention function and a control gate structure for applying an electric field to a channel via the floating gate structure, stacked on a semiconductor region formed with the channel. The floating gate structure includes a silicon layer insulated with an insulating layer or layers, or a lamination of an oxide film, a nitride film and an oxide film, forming a nitride film interface having a charge storage function.
Programming (data write) is performed by selectively injecting electrons into the floating gate. When a predetermined voltage is applied to the control gate structure, the conductivity of a channel below the floating gate changes, depending on whether or not there are charges in the floating gate structure. Hence, written information can be read. By draining electrons from the floating gate structure, written information can be erased.
It is preferable to cover the side walls of the floating gate structure with an insulating film of good quality, in order to reduce leak of charges written in the floating gate structure. For example, a floating electrode is formed by a silicon layer sandwiched between insulating layers, and side walls are thermally oxidized. A floating gate electrode covered with an insulating film of good quality such as a thermally oxidized film improves the charge retention performance. The charge retention performance of a floating gate structure made of a lamination of oxide film-nitride film-oxide film can also be improved by covering the side walls with an oxide film or the like.
A semiconductor integrated circuit such as a system LSI of high integration degree is structured having a plurality type of semiconductor elements such as non-volatile memories, high voltage insulated gate field effect (abbreviated to MOS) transistors for driving them and low voltage MOS transistors for logical circuits. A logical circuit low voltage MOS transistor has a short gate length and a thin gate insulating film in order to raise its operation speed.
Manufacture processes for a semiconductor integrated circuit are designed to use in common as many same processes as possible for the manufacture of a plurality type of semiconductor elements. For example, the gate electrode of a MOS transistor is made of the same silicon layer as that of the control gate electrode of a non-volatile memory cell.
In the process of thermally oxidizing the side walls of a floating gate electrode, the side walls of the gate electrode of a MOS transistor are also thermally oxidized. During the thermally oxidizing process, oxidizing species enter the interface between a silicon substrate and an upper insulating film and the interface between a silicon layer and an insulating film so that an oxidized region called a bird's beak is formed.
A low voltage MOS transistor has a short gate length and a thin gate insulating film. As a birds' beak is formed at the edge portions of a gate insulating film, the gate insulating film becomes thick under the edge portions of the gate electrode so that a drive current of the MOS transistor is lowered.
A laminated gate structure of a non-volatile memory cell and a single layer gate structure of a MOS transistor are patterned by using different masks and different processes. Therefore, mask alignment margins are increased. If a first mask alignment margin is 0.2 μm, a second mask alignment margin is increased to 0.28 μm. An increase in the mask alignment margin hinders high integration.
Japanese Patent Laid-open Publication No. HEI-10-223782 proposes a non-volatile memory cell whose control gate electrode is made of a diffusion region in a substrate. A low resistance region functioning as a control gate electrode is formed in a semiconductor substrate, and a floating gate electrode is formed extending from an area above a channel region of the memory transistor to an area above the low resistance region functioning as the control gate electrode. The control gate electrode can be formed by the same process as that for the source/drain regions of the memory transistor, so that the manufacture processes for a non-volatile memory can be simplified.